Automatic test systems are used to test electronic products. FIG. 1 is a block diagram showing a simplified view of an example of a conventional automatic test system 10. Test system 10 is composed of a system controller 12, a number of test instruments 14 and a test fixture 16. Test fixture 16 provides an interface that allows test system 10 to exchange signals with a unit under test (UUT). System controller 12 is connected to a control port of each of the test instruments 14 via a suitable communication link or network such as GPIB or, more typically, via an Ethernet local area network 18. System controller 12 is additionally connected to the UUT via test fixture 16 and network 18. Test instruments 14 operate in response to commands output by system controller 12 to monitor or control various inputs and outputs of unit under test UUT via test fixture 16. In the example shown, the test instruments are indicated by the same reference numeral 14 but in practice the test instruments that constitute automatic test system 10 differ from one another. The number of test instruments may differ from the number in the example shown. Exemplary ones of the test instruments 14 are indicated at 22 and 24.
An automatic test system such as automatic test system 10 tests a UUT by subjecting the UUT to a sequence of tests. Such sequence of tests will be referred to as a test sequence. In each test in the test sequence, the automatic test system measures the response of the UUT to a stimulus, and compares the response to one or more test limits to determine whether the unit under test has passed or failed the test. The stimulus is typically generated by one of the test instruments 14 constituting test system 10 but may additionally or alternatively be provided by a source external to test system 10. Passing the test typically causes the automatic test system to subject the UUT to the next test in the test sequence. Failing the test may cause the automatic test system to stop testing the unit under test. Alternatively, the automatic test system may repeat the failed test and only stop the testing if the UUT fails the test a predetermined number of times consecutively.
FIG. 2 is a flow chart illustrating a portion of a typical test sequence 30 performed by conventional automatic test system 10 described above with reference to FIG. 1. In block 32, system controller 12 issues commands that configure test instruments 14 to perform a test n. For example, in block 32, the command issued by system controller 12 defines the parameters of a stimulus that will be generated by test instrument 22 and additionally defines a set of measurement parameters that will be used by test instrument 24 to measure the response of the UUT to the stimulus.
In block 34, system controller 12 issues a command that causes test instruments 14 to perform test n. For example, in block 34, the command issued by system controller 12 causes test instrument 22 to generate the stimulus defined in block 32 and to apply such stimulus to the UUT via test fixture 16. The command additionally causes test instruments 24 to receive a response of the UUT to the stimulus via test fixture 16 and to measure the response using the specified measurement parameters.
In block 36, a test is performed to determine whether the UUT has passed test n. For example, in block 36, system controller 12 issues a command that causes test instrument 24 to compare the measurement made in block 34 with a predetermined test limit. The command additionally causes test instrument 24 to return a test result YES when the measurement is within the test limit, otherwise to return a test result NO, and to output the test result to system controller 12. The test result received by system controller 12 determines the future course of the test sequence.
A YES result received by system controller 12 in block 36 causes automatic test system 10 to perform blocks 42 and 44. Blocks 42 and 44 are similar to blocks 32 and 34, respectively, and respectively cause test system 10 to configure itself to perform a test n+1 and to apply test n+1 to the UUT. Blocks 42 and 44 will not be described further.
A NO result in block 36 causes automatic test system 10 to perform block 38. In block 38, controller 12 determines whether the UUT has failed test n a predetermined number m of times.
A YES result in block 38 causes the test sequence to end. A NO result in block 38 causes execution to return to block 34, where test n is executed again. Execution of the loop composed of blocks 34, 36 and 38 continues until a YES result is obtained in block 36 (test n+1 then executes) or a YES result is obtain in block 38 (test sequence then ends).
As electronic products have become more complex, the time required for the automatic test system to test each unit under test has increased. Moreover, the cost of the constituent components of the electronic products has fallen. Consequently, the fraction of the cost of manufacture represented by the cost of testing has undesirably increased.
What is needed is a way to reduce the cost of testing an electronic product.